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si5345/44/42 rev d data sheet 10-channel, any-frequency, any-output jitter attenuator/ clock multiplier these jitter attenuating clock multipliers combine fourth-generation dspll ? and multisynth ? technologies to enable any-frequency clock generation and jitter attenu- ation for applications requiring the highest level of jitter performance. these devices are programmable via a serial interface with in-circuit programmable non-volatile memory (nvm) so they always power up with a known frequency configuration. they support free-run, synchronous, and holdover modes of operation, and offer both au- tomatic and manual input clock switching. the loop filter is fully integrated on-chip, eliminating the risk of noise coupling associated with discrete solutions. furthermore, the jitter attenuation bandwidth is digitally programmable, providing jitter perform- ance optimization at the application level. programming the si5345/44/42 is easy with silicon labs clockbuilder pro ? software. factory preprogrammed devices are also available. applications: ? otn muxponders and transponders ? 10/40/100 g networking line cards ? gbe/10 gbe/100 gbe synchronous ethernet (itu-t g.8262) ? carrier ethernet switches ? sonet/sdh line cards ? broadcast video ? test and measurement ? itu-t g.8262 (synce) compliant key features ? generates any combination of output frequencies from any input frequency ? ultra-low jitter of 90 fs rms ? external crystal: 25 to 54 mhz ? input frequency range ? differential: 8 khz to 750 mhz ? lvcmos: 8 khz to 250 mhz ? output frequency range ? differential: 100 hz to 1028 mhz ? lvcmos: 100 hz to 250 mhz ? meets g.8262 eec option 1, 2 (synce) ? highly configurable outputs compatible with lvds, lvpecl, lvcmos, cml, and hcsl with programmable signal amplitude ? si5345: 4 input, 10 output, 64-qfn 99 mm ? si5344: 4 input, 4 output, 44-qfn 77 mm ? si5342: 4 input, 2 output, 44-qfn 77 mm up to 10 output clocks si5344 si5345 i2c / spi control nvm status flags status monitor xb xa 25-54 mhz xtal osc multisynth multisynth multisynth multisynth multisynth int int int dspll int si5342 4 input clocks in0 in1 in2 in3/fb_in out7 out6 out5 out1 out4 out3 out2 out0 int int int int int int int int out9 out8 int int silabs.com | smart. connected. energy-friendly. rev. 1.0
1. features list the si5345/44/42 rev d features are listed below: ? generates any combination of output frequencies from any in- put frequency ? ultra-low jitter of 90 fs rms ? input frequency range ? differential: 8 khzC750 mhz ? lvcmos: 8 khzC250 mhz ? output frequency range ? differential: 100 hz to 1028 mhz ? lvcmos: 100 hz to 250 mhz ? programmable jitter attenuation bandwidth: 0.1 hz to 4 khz ? meets g.8262 eec option 1, 2 (synce) ? highly configurable outputs compatible with lvds, lvpecl, lvcmos, cml, and hcsl with programmable signal ampli- tude ? status monitoring (los, oof, lol) ? hitless input clock switching: automatic or manual ? locks to gapped clock inputs ? free-run and holdover modes ? optional zero delay mode ? fastlock feature for low nominal bandwidths ? glitchless on the fly output frequency changes ? dco mode: as low as 0.001 ppb step size ? core voltage ? v dd : 1.8 v 5% ? v dda : 3.3 v 5% ? independent output clock supply pins ? 3.3 v, 2.5 v, or 1.8 v ? serial interface: i 2 c or spi ? in-circuit programmable with non-volatile otp memory ? clockbuilder pro software simplifies device configuration ? si5345: 4 input, 10 output, 64-qfn 99 mm ? si5344: 4 input, 4 output, 44-qfn 77 mm ? si5342: 4 input, 2 output, 44-qfn 77 mm ? temperature range: C40 to +85 c ? pb-free, rohs-6 compliant si5345/44/42 rev d data sheet features list silabs.com | smart. connected. energy-friendly. rev. 1.0 | 1
2. ordering guide ordering part number (opn) number of input/ output clocks output clock frequency range (mhz) supported frequency synthesis modes package temperature range si5345 si5345a-d-gm 1, 2 4/10 0.001 to 1028 mhz integer and fractional 64-qfn 99 mm C40 to 85 c si5345b-d-gm 1, 2 0.001 to 350 mhz si5345c-d-gm 1, 2 0.001 to 1028 mhz integer only si5345d-d-gm 1, 2 0.001 to 350 mhz si5344 si5344a-d-gm 1 , 2 4/4 0.001 to 1028 mhz integer and fractional 44-qfn 77 mm C40 to 85 c si5344b-d-gm 1, 2 0.001 to 350 mhz si5344c-d-gm 1, 2 0.001 to 1028 mhz integer only si5344d-d-gm 1, 2 0.001 to 350 mhz si5342 si5342a-d-gm 1 , 2 4/2 0.001 to 1028 mhz integer and fractional 44-qfn 77 mm C40 to 85 c si5342b-d-gm 1, 2 0.001 to 350 mhz si5342c-d-gm 1, 2 0.001 to 1028 mhz integer only si5342d-d-gm 1, 2 0.001 to 350 mhz si5345/44/42-d-evb si5345-d-evb evaluation board SI5344-D-EVB si5342-d-evb notes: 1. add an r at the end of the opn to denote tape and reel ordering options. 2. custom, factory preprogrammed devices are available. ordering part numbers are assigned by silicon labs and the clockbuilder pro software utility. custom part number format is si5345a-dxxxxx-gm where xxxxx is a unique numerical sequence repre- senting the preprogrammed configuration. si5345/44/42 rev d data sheet ordering guide silabs.com | smart. connected. energy-friendly. rev. 1.0 | 2
figure 2.1. ordering part number fields si5345/44/42 rev d data sheet ordering guide silabs.com | smart. connected. energy-friendly. rev. 1.0 | 3
3. functional description the si5345s internal dspll provides jitter attenuation and any-frequency multiplication of the selected input frequency. fractional in- put dividers (p) allow the dspll to perform hitless switching between input clocks (inx) that are fractionally related. input switching is controlled manually or automatically using an internal state machine. the oscillator circuit (osc) provides a frequency reference which determines output frequency stability and accuracy while the device is in free-run or holdover mode. the high-performance multisynth dividers (n) generate integer or fractionally related output frequencies for the output stage. a crosspoint switch connects any of the multisynth generated frequencies to any of the outputs. additional integer division (r) determines the final output frequency. 3.1 frequency configuration the frequency configuration of the dspll is programmable through the serial interface and can also be stored in non-volatile memory. the combination of fractional input dividers (p n /p d ), fractional frequency multiplication (m n /m d ), fractional output multisynth division (n n /n d ), and integer output division (r n ) allows the generation of virtually any output frequency on any of the outputs. all divider values for a specific frequency plan are easily determined using the clockbuilder pro utility. 3.2 dspll loop bandwidth the dspll loop bandwidth determines the amount of input clock jitter attenuation. register configurable dspll loop bandwidth set- tings in the range of 0.1 hz to 4 khz are available for selection. since the loop bandwidth is controlled digitally, the dspll will always remain stable with less than 0.1 db of peaking regardless of the loop bandwidth selection. 3.3 fastlock feature selecting a low dspll loop bandwidth (e.g. 0.1 hz) will generally lengthen the lock acquisition time. the fastlock feature allows setting a temporary fastlock loop bandwidth that is used during the lock acquisition process. higher fastlock loop bandwidth settings will ena- ble the dsplls to lock faster. fastlock loop bandwidth settings of in the range of 100 hz to 4 khz are available for selection. the dspll will revert to its normal loop bandwidth once lock acquisition has completed. 3.4 modes of operation once initialization is complete the dspll operates in one of four modes: free-run mode, lock acquisition mode, locked mode, or holdover mode. a state diagram showing the modes of operation is shown in figure 3.1 modes of operation on page 5 . the follow- ing sections describe each of these modes in greater detail. si5345/44/42 rev d data sheet functional description silabs.com | smart. connected. energy-friendly. rev. 1.0 | 4
3.4.1 initialization and reset once power is applied, the device begins an initialization period where it downloads default register values and configuration data from nvm and performs other initialization tasks. communicating with the device through the serial interface is possible once this initializa- tion period is complete. no clocks will be generated until the initialization is complete. there are two types of resets available. a hard reset is functionally similar to a device power-up. all registers will be restored to the values stored in nvm, and all circuits including the serial interface will be restored to their initial state. a hard reset is initiated using the rstb pin or by asserting the hard reset register bit. a soft reset bypasses the nvm download. it is simply used to initiate register configuration changes. no valid input clocks selected lock acquisition (fast lock) locked mode holdover mode phase lock on selected input clock is achieved an input is qualified and available for selection no valid input clocks available for selection free-run valid input clock selected reset and initialization power-up selected input clock fails yes no holdover history valid? other valid clock inputs available? no yes input clock switch figure 3.1. modes of operation 3.4.2 freerun mode the dspll will automatically enter freerun mode once power is applied to the device and initialization is complete. the frequency ac- curacy of the generated output clocks in freerun mode is entirely dependent on the frequency accuracy of the external crystal or refer- ence clock on the xa/xb pins. for example, if the crystal frequency is 100 ppm, then all the output clocks will be generated at their configured frequency 100 ppm in freerun mode. any drift of the crystal frequency will be tracked at the output clock frequencies. a tcxo or ocxo is recommended for applications that need better frequency accuracy and stability while in freerun or holdover modes. 3.4.3 lock acquisition mode the device monitors all inputs for a valid clock. if at least one valid clock is available for synchronization, the dspll will automatically start the lock acquisition process. if the fast lock feature is enabled, the dspll will acquire lock using the fastlock loop bandwidth setting and then transition to the dspll loop bandwidth setting when lock acquisition is complete. during lock acquisition the outputs will generate a clock that follows the vco frequency change as it pulls in to the input clock frequency. 3.4.4 locked mode once locked, the dspll will generate output clocks that are both frequency and phase locked to their selected input clocks. at this point, any xtal frequency drift will not affect the output frequency. a loss of lock pin (lol) and status bit indicate when lock is ach- ieved. see 3.8.4 lol detection for more details on the operation of the loss-of-lock circuit. si5345/44/42 rev d data sheet functional description silabs.com | smart. connected. energy-friendly. rev. 1.0 | 5
3.4.5 holdover mode the dspll will automatically enter holdover mode when the selected input clock becomes invalid and no other valid input clocks are available for selection. the dspll uses an averaged input clock frequency as its final holdover frequency to minimize the disturbance of the output clock phase and frequency when an input clock suddenly fails. the holdover circuit for the dspll stores up to 120 sec- onds of historical frequency data while locked to a valid clock input. the final averaged holdover frequency value is calculated from a programmable window within the stored historical frequency data. both the window size and the delay are programmable as shown in the figure below. the window size determines the amount of holdover frequency averaging. the delay value allows ignoring frequency data that may be corrupt just before the input clock failure. programmable delay clock failure and entry into holdover time 0s historical frequency data collected programmable historical data window used to de t ermine the final holdover value 120s 1s,10s, 30s, 60s 30ms, 60ms, 1s,10s, 30s, 60s figure 3.2. programmable holdover window when entering holdover, the dspll will pull its output clock frequency to the calculated averaged holdover frequency. while in hold- over, the output frequency drift is entirely dependent on the external crystal or external reference clock connected to the xa/xb pins. if the clock input becomes valid, the dspll will automatically exit the holdover mode and re-acquire lock to the new input clock. this process involves pulling the output clock frequency to achieve frequency and phase lock with the input clock. this pull-in process is glitchless and its rate is controlled by the dspll or the fastlock bandwidth. the dspll output frequency when exiting holdover can be ramped (recommend). just before the exit is initiated, the difference be- tween the current holdover frequency and the new desired frequency is measured. using the calculated difference and a user-selecta- ble ramp rate, the output is linearly ramped to the new frequency. the ramp rate can be 0.2 ppm/s, 40,000 ppm/s, or any of about 40 values in between. the dspll loop bw does not limit or affect ramp rate selections (and vice versa). cbpro defaults to ramped exit from holdover. the same ramp rate settings are used for both exit from holdover and ramped input switching. for more information on ramped input switching, see 3.7.4 ramped input switching . note: if ramped holdover exit is not selected, the holdover exit is governed either by (1) the dspll loop bw or (2) a user-selectable holdover exit bw. 3.5 external reference (xa/xb) an external crystal (xtal) is used in combination with the internal oscillator (osc) to produce an ultra low jitter reference clock for the dspll and for providing a stable reference for the free-run and holdover modes. a simplified diagram is shown in figure 3.3 crystal resonator and external reference clock connection options on page 7 . the device includes internal xtal loading capacitors which eliminates the need for external capacitors and also has the benefit of reduced noise coupling from external sources. refer to table 5.12 crystal specifications on page 36 for crystal specifications. a crystal in the range of 48 mhz to 54 mhz is recommended for best jitter performance. frequency offsets due to cl mismatch can be adjusted using the frequency adjustment feature which allows frequency adjustments of 200 ppm. the si5345/44/42 family reference manual provides additional information on pcb layout recom- mendations for the crystal to ensure optimum jitter performance. to achieve optimal jitter performance and minimize bom cost, a crystal is recommended on the xa/xb reference input. for synce line card pll applications (e.g. loop bandwidth set to 0.1 hz), a tcxo is required on the xa/xb reference to minimize wander and to pro- vide a stable holdover reference. see the si5345/44/42 family reference manual for more information. selection between the external xtal or refclk is controlled by register configuration. the internal crystal loading capacitors (cl) are disabled in the refclk mode. refer to table 5.3 input clock specifications on page 25 for refclk requirements when using this mode. a pref divider is availa- ble to accommodate external clock frequencies higher than 54 mhz. frequencies in the range of 48 mhz to 54 mhz will achieve the best output jitter performance. si5345/44/42 rev d data sheet functional description silabs.com | smart. connected. energy-friendly. rev. 1.0 | 6
3.6 digitally controlled oscillator (dco) mode the output multisynths support a dco mode where their output frequencies are adjustable in predefined steps defined by frequency step words (fsw). the frequency adjustments are controlled through the serial interface or by pin control using frequency increment (finc) or decrement (fdec). a finc will add the frequency step word to the dspll output frequency, while a fdec will decrement it. any number of multisynths can be updated at once or independently controlled. the dco mode is available when the dspll is operat- ing in either free-run or locked mode. osc xb xa 25-54mhz xtal 2c l 2cl crystal resonator connection osc xb xa 25-54mhz xo 100 differential xo connection osc xb xa 25-54mhz xo single-ended xo connection 2c l 2c l 2c l si5345/44/42 2c l p ref p ref p ref si5345/44/42 si5345/44/42 figure 3.3. crystal resonator and external reference clock connection options 3.7 inputs (in0, in1, in2, in3) there are four inputs that can be used to synchronize the dspll. the inputs accept both differential and single-ended clocks. input selection can be manual (pin or register controlled) or automatic with user definable priorities. si5345/44/42 rev d data sheet functional description silabs.com | smart. connected. energy-friendly. rev. 1.0 | 7
3.7.1 manual input switching (in0, in1, in2, in3) input clock selection can be made manually using the in_sel[1:0] pins or through a register. a register bit determines input selection as pin selectable or register selectable. the in_sel pins are selected by default. if there is no clock signal on the selected input, the device will automatically enter free-run or holdover mode. when the zero delay mode is enabled, in3 becomes the feedback input (fb_in) and is not available for selection as a clock input. table 3.1. manual input selection using in_sel[1:0] pins in_sel[1:0] selected input zero delay mode disabled zero delay mode enabled 0 0 in0 in0 0 1 in1 in1 1 0 in2 in2 1 1 in3 reserved 3.7.2 automatic input selection (in0, in1, in2, in3) an automatic input selection state machine is available in addition to the manual switching option. in automatic mode, the selection criteria is based on input clock qualification, input priority, and the revertive option. only input clocks that are valid can be selected by the automatic clock selection state machine. if there are no valid input clocks available the dspll will enter the holdover mode. with revertive switching enabled, the highest priority input with a valid input clock is always selected. if an input with a higher priority be- comes valid then an automatic switchover to that input will be initiated. with non-revertive switching, the active input will always remain selected while it is valid. if it becomes invalid an automatic switchover to a valid input with the highest priority will be initiated. 3.7.3 hitless input switching hitless switching is a feature that prevents a phase offset from propagating to the output when switching between two clock inputs that have a fixed phase relationship. a hitless switch can only occur when the two input frequencies are frequency locked meaning that they have to be exactly at the same frequency, or at a fractional frequency relationship to each other. when hitless switching is enabled, the dspll simply absorbs the phase difference between the two input clocks during a input switch. when disabled, the phase difference between the two inputs is propagated to the output at a rate determined by the dspll loop bandwidth. the hitless switching feature supports clock frequencies down to the minimum input frequency of 8 khz. 3.7.4 ramped input switching when switching between two plesiochronous input clocks (i.e., the frequencies are "almost the same" but not quite), ramped input switching should be enabled to ensure a smooth transition between the two inputs. ramped input switching avoids frequency transients and overshoot when switching between frequencies and so is the default switching mode in cbpro. the feature should be turned off when switching between input clocks that are always frequency locked (i.e., are always the same exact frequency). the same ramp rate settings are used for both holdover exit and clock switching. for more information on ramped exit from holdover see 3.4.5 holdover mode . 3.7.5 glitchless input switching the dspll has the ability of switching between two input clock frequencies that are up to 500 ppm apart. the dspll will pull-in to the new frequency using the dspll loop bandwidth or using the fastlock loop bandwidth if enabled. the loss of lock (lol) indicator will assert while the dspll is pulling-in to the new clock frequency. there will be no abrupt phase change at the output during the transi- tion. si5345/44/42 rev d data sheet functional description silabs.com | smart. connected. energy-friendly. rev. 1.0 | 8
3.7.6 input configuration and terminations each of the inputs can be configured as differential or single-ended lvcmos. the recommended input termination schemes are shown in figure 14. differential signals must be ac-coupled, while single-ended lvcmos signals can be ac or dc-coupled. unused inputs can be disabled and left unconnected when not in use. pulsed cmos dc coupled single ended standard ac coupled single ended 100 3.3v, 2.5v, 1.8v l vcmos standard ac coupled differential lvpecl inx inxb 50 100 standard ac coupled differential lvds inx inxb 3.3v , 2.5v l vpecl 3.3v , 2.5v l vds or cml inx inxb inx inxb 50 50 50 50 pulsed cmos standard si5345/44/42 si5345/44/42 si5345/44/42 si5345/44/42 3.3v , 2.5v, 1.8v l vcmos 50 r 2 r1 pulsed cmos standard pulsed cmos standard pulsed cmos standard vdd r1 (ohm) r2 (ohm) 1.8 v 2.5 v 3.3 v 324 51 1 634 665 475 365 figure 3.4. termination of differential and lvcmos input signals si5345/44/42 rev d data sheet functional description silabs.com | smart. connected. energy-friendly. rev. 1.0 | 9
3.7.7 synchronizing to gapped input clocks the dspll supports locking to an input clock that has missing periods. this is also referred to as a gapped clock. the purpose of gapped clocking is to modulate the frequency of a periodic clock by selectively removing some of its cycles. gapping a clock severely increases its jitter so a phase-locked loop with high jitter tolerance and low loop bandwidth is required to produce a low-jitter periodic clock. the resulting output will be a periodic non-gapped clock with an average frequency of the input with its missing cycles. for example, an input clock of 100 mhz with one cycle removed every 10 cycles will result in a 90 mhz periodic non-gapped output clock. this is shown in the following figure. for more information on gapped clocks, see an561: introduction to gapped clocks and plls. dspll 100 ns 100 ns 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 100 mhz clock 1 missi ng per iod every 10 90 mhz non-gapped clock 10 ns 11.11111... ns gapped input clock periodic output clock period removed figure 3.5. generating an averaged clock output frequency from a gapped clock input a valid gapped clock input must have a minimum frequency of 10 mhz with a maximum of two missing cycles out of every eight. lock- ing to a gapped clock will not trigger the los, oof, and lol fault monitors. clock switching between gapped clocks may violate the hitless switching specification in table 5.8 performance characteristics on page 31 when the switch occurs during a gap in either input clock. 3.8 fault monitoring all four input clocks (in0, in1, in2, in3/fb_in) are monitored for loss of signal (los) and out-of-frequency (oof) as shown in the fig- ure below. the reference at the xa/xb pins is also monitored for los since it provides a critical reference clock for the dspll. there is also a loss of lock (lol) indicator which is asserted when the dspll loses synchronization. dspll lpf pd m in0 in0b precision fast oof los p 0 in1 in1b precision fast oof los p 1 in3/fb_in in3/fb_inb precision fast oof los p 3 in2 in2b precision fast oof los p 2 lol xb xa osc los si5345/44/42 figure 3.6. si5345/44/42 fault monitors si5345/44/42 rev d data sheet functional description silabs.com | smart. connected. energy-friendly. rev. 1.0 | 10
3.8.1 input los detection the loss of signal monitor measures the period of each input clock cycle to detect phase irregularities or missing clock edges. each of the input los circuits has its own programmable sensitivity which allows ignoring missing edges or intermittent errors. loss of signal sensitivity is configurable using the clockbuilder pro utility. the los status for each of the monitors is accessible by reading a status register. the live los register always displays the current los state and a sticky register always stays asserted until cleared. an option to disable any of the los monitors is also available. los en monitor los los sticky live figure 3.7. los status indicators 3.8.2 xa/xb los detection a los monitor is available to ensure that the external crystal or reference clock is valid. by default the output clocks are disabled when xaxb_los is detected. this feature can be disabled such that the device will continue to produce output clocks when xaxb_los is detected. 3.8.3 oof detection each input clock is monitored for frequency accuracy with respect to a oof reference which it considers as its 0_ppm reference. this oof reference can be selected as either: ? xa/xb pins ? any input clock (in0, in1, in2, in3) the final oof status is determined by the combination of both a precise oof monitor and a fast oof monitor as shown in the figure below. an option to disable either monitor is also available. the live oof register always displays the current oof state, and its sticky register bit stays asserted until cleared. precision fast oof monitor los oof sticky live figure 3.8. oof status indicator si5345/44/42 rev d data sheet functional description silabs.com | smart. connected. energy-friendly. rev. 1.0 | 11
3.8.3.1 precision oof monitor the precision oof monitor circuit measures the frequency of all input clocks to within 1/16 ppm accuracy with respect to the selected oof frequency reference. a valid input clock frequency is one that remains within the oof frequency range which is register configura- ble up to 500 ppm in steps of 1/16 ppm. a configurable amount of hysteresis is also available to prevent the oof status from toggling at the failure boundary. an example is shown in the figure below. in this case, the oof monitor is configured with a valid frequency range of 6 ppm and with 2 ppm of hysteresis. an option to use one of the input pins (in0Cin3) as the 0 ppm oof reference instead of the xa/xb pins is available. this option is register configurable. oof reference hysteresis hysteresis oof declared oof cleared -6 ppm (set) -4 ppm (clear ) 0 ppm +4 ppm (clear) +6 ppm (set) f in figure 3.9. example of precise oof monitor assertion and deassertion triggers 3.8.3.2 fast oof monitor because the precision oof monitor needs to provide 1/16 ppm of frequency measurement accuracy, it must measure the monitored input clock frequencies over a relatively long period of time. this may be too slow to detect an input clock that is quickly ramping in frequency. an additional level of oof monitoring called the fast oof monitor runs in parallel with the precision oof monitors to quick- ly detect a ramping input frequency. the fast oof monitor asserts oof on an input clock frequency that has changed by greater than 4000 ppm. 3.8.4 lol detection the loss of lock (lol) monitor asserts a lol register bit when the dspll has lost synchronization with its selected input clock. there is also a dedicated loss of lock pin that reflects the loss of lock condition. the lol monitor functions by measuring the frequency difference between the input and feedback clocks at the phase detector. there are two lol frequency monitors, one that sets the lol indicator (lol set) and another that clears the indicator (lol clear). an optional timer is available to delay clearing of the lol indicator to allow additional time for the dspll to completely lock to the input clock. the timer is also useful to prevent the lol indicator from toggling or chattering as the dspll completes lock acquisition. a block diagram of the lol monitor is shown in the figure below. the live lol register always displays the current lol state and a sticky register always stays asserted until cleared. the lol pin reflects the current state of the lol monitor. dspll lpf pd m si5345/44/42 lol clear lol set timer lolb los lol sticky live lol monitor f in feedback clock figure 3.10. lol status indicators the lol frequency monitors have an adjustable sensitivity which is register configurable from 0.1 ppm to 10,000 ppm. having two sep- arate frequency monitors allows for hysteresis to help prevent chattering of lol status. si5345/44/42 rev d data sheet functional description silabs.com | smart. connected. energy-friendly. rev. 1.0 | 12
an example configuration where lock is indicated when there is less than 0.1 ppm frequency difference at the inputs of the phase detector and lol is indicated when theres more than 1 ppm frequency difference is shown in the following figure. phase detector frequency difference (ppm) hysteresis lol locked clear lol threshold set lol threshold lock acquisition 0 lost lock 10,000 0.1 1 bb ii p m fm oo p in this document, the terms, lvds and lvpecl, refer to driver formats that are compatible with these signaling standards. an optional timer is available to delay clearing of the lol indicator to allow additional time for the dspll to completely lock to the input clock. the timer is also useful to prevent the lol indicator from toggling or chattering as the dspll completes lock acquisition. the configurable delay value depends on frequency configuration and loop bandwidth of the dspll and is automatically calculated using the clockbuilder pro utility. 3.8.5 interrupt pin (intrb) an interrupt pin (intrb) indicates a change in state of the status indicators (los, oof, lol, hold). any of the status indicators are maskable to prevent assertion of the interrupt pin. the state of the intrb pin is reset by clearing the status register that caused the interrupt. 3.9 outputs each driver has a configurable voltage swing and common mode voltage covering a wide variety of differential signal formats. in addi- tion to supporting differential signals, any of the outputs can be configured as single-ended lvcmos (3.3 v, 2.5 v, or 1.8 v) providing up to 20 single-ended outputs, or any combination of differential and single-ended outputs. si5345/44/42 rev d data sheet functional description silabs.com | smart. connected. energy-friendly. rev. 1.0 | 13
3.9.1 output crosspoint a crosspoint allows any of the output drivers to connect with any of the multisynths as shown in the figure below. the crosspoint config- uration is programmable and can be stored in nvm so that the desired output configuration is ready at power up. out2b vddo2 out2 vddo3 vddo0 out0b out0 r 2 out3b out3 r 3 out1b vddo1 out1 r 1 out5b vddo5 out5 vddo6 r 5 out6b out6 r 6 out4b vddo4 out4 r 4 out7b vddo7 out7 vddo8 r 7 out8b out8 r 8 r 0 multi synth n 0n n 0d multi synth multi synth multi synth n 2n n 2d n 3n n 3d n 4n n 4d multi synth n 1n n 1d t 0 t 1 t 2 t 3 t 4 out9b out9 r 9 vddo9 figure 3.12. multisynth to output driver crosspoint 3.9.2 output signal format the differential output swing and common mode voltage are both fully programmable covering a wide variety of signal formats including lvds and lvpecl. in addition to supporting differential signals, any of the outputs can be configured as lvcmos (3.3 v, 2.5 v, or 1.8 v) drivers providing up to 20 single-ended outputs, or any combination of differential and single-ended outputs. si5345/44/42 rev d data sheet functional description silabs.com | smart. connected. energy-friendly. rev. 1.0 | 14
3.9.3 differential output terminations the differential output drivers support both ac-coupled and dc-coupled terminations as shown in the figure below. note: in this document, the terms, lvds and lvpecl, refer to driver formats that are compatible with these signaling standards. 100 50 50 internally self-biased ac coupled lvds/lvpecl 50 50 ac coupled lvpecl vdd C 1.3v 50 50 50 50 100 dc coupled lvds/lvpecl outx outxb outx outxb outx outxb v ddo = 3. 3 v, 2.5v, 1.8v v ddo = 3.3v, 2.5v v ddo = 3.3v, 2.5v, 1.8v si5345/44/42 si5345/44/42 si5345/44/42 figure 3.13. supported differential output terminations 3.9.4 lvcmos output terminations lvcmos outputs are dc-coupled, as shown in the following figure. [/ah v ddo = 3. 3 v, 2.5v, 1.8v 50 rs 50 rs dc coupled lvcmos outx outxb si5345/44/42 figure 3.14. lvcmos output terminations 3.9.5 programmable common mode voltage for differential outputs the common mode voltage (v cm ) for the differential modes are programmable so that lvds specifications can be met and for the best signal integrity with different supply voltages. when dc coupling the output driver, it is essential that the receiver have a relatively high common mode impedance so that the common mode current from the output driver is very small. si5345/44/42 rev d data sheet functional description silabs.com | smart. connected. energy-friendly. rev. 1.0 | 15
3.9.6 lvcmos output impedance selection each lvcmos driver has a configurable output impedance to accommodate different trace impedances. a source termination resistor is recommended to help match the selected output impedance to the trace impedance, where rs = transmission line impedance C z o . there are three programmable output impedance selections (cmos1, cmos2, cmos3) for each vddo option as shown in the follow- ing table. table 3.2. typical output impedance (z s ) vddo cmos drive selections outx_cmos_drv = 1 outx_cmos_drv = 2 outx_cmos_drv = 3 3.3 v 38 30 22 2.5 v 43 35 24 1.8 v 46 31 3.9.7 lvcmos output signal swing the signal swing (v ol /v oh ) of the lvcmos output drivers is set by the voltage on the vddo pins. each output driver has its own vddo pin allowing a unique output voltage swing for each of the lvcmos drivers. 3.9.8 lvcmos output polarity when a driver is configured as an lvcmos output, it generates a clock signal on both pins (outx and outxb). by default, the clock on the outx pin is generated with the same polarity (in phase) as the clock on the outxb pin. the polarity of these clocks is configura- ble, enabling complementary clock generation and/or inverted polarity with respect to other output drivers. 3.9.9 output enable/disable the oeb pin provides a convenient method of disabling or enabling the output drivers. when the oeb pin is held high, all outputs are disabled. when held low, the outputs are enabled. outputs in the enabled state can be individually disabled through register control. 3.9.10 output driver state when disabled the disabled state of an output driver is configurable as disable low or disable high. 3.9.11 synchronous output disable feature the output drivers provide a selectable synchronous disable feature. output drivers with this feature turned on will wait until a clock period has completed before the driver is disabled. this prevents unwanted runt pulses from occurring when disabling an output. when this feature is turned off, the output clock will disable immediately without waiting for the period to complete. si5345/44/42 rev d data sheet functional description silabs.com | smart. connected. energy-friendly. rev. 1.0 | 16
3.9.12 output skew control (t 0 C t 4 ) the si5345/44/42 uses independent multisynth dividers (n 0 C n 4 ) to generate up to five unique frequencies to its ten outputs through a crosspoint switch. by default, all clocks are phase-aligned. a delay path (t 0 C t 4 ) associated with each of these dividers is available for applications that need a specific output skew configuration. this is useful for pcb trace length mismatch compensation. the resolu- tion of the phase adjustment is approximately 0.28 ps per step, definable in a range of 9.14 ns. phase adjustments are register-config- urable. an example of generating two frequencies with unique configurable path delays is shown in the following figure. n 0 t 0 n 1 t 1 n 2 t 2 n 3 t 3 n 4 t 4 out2b vddo2 out2 vddo3 r 2 out3b out3 r 3 out1b vddo1 out1 r 1 out5b vddo5 out5 vddo6 r 5 out6b out6 r 6 out4b vddo4 out4 r 4 out7b vddo7 out7 vddo8 r 7 out8b out8 r 8 out0b vddo0 out0 r 0 vddo9 out9b out9 r 9 figure 3.15. example of independently-configurable path delays all phase delay values are restored to their default values after power-up, hard reset, or a reset using the rstb pin. phase delay de- fault values can be written to nvm, allowing a custom phase offset configuration at power-up or after power-on reset, or after a hard- ware reset using the rstb pin. si5345/44/42 rev d data sheet functional description silabs.com | smart. connected. energy-friendly. rev. 1.0 | 17
3.9.13 zero delay mode a zero delay mode is available for applications that require fixed and consistent minimum delay between the selected input and outputs. the zero delay mode is configured by opening the internal feedback loop through software configuration and closing the loop externally as shown in the figure below. this helps to cancel out the internal delay introduced by the dividers, the crosspoint, the input, and the output drivers. any one of the outputs can be fed back to the fb_in pins, although using the output driver that achieves the shortest trace length will help to minimize the input-to-output delay. the out9 and fb_in pins are recommended for the external feedback connection. the fb_in input pins must be terminated and ac-coupled when zero delay mode is used. a differential external feedback path connection is necessary for best performance. note that the hitless switching feature is not available when zero delay mode is enabled. vddo7 out7b out7 r 7 out0b vddo0 out0 r 0 si5345/44/42 in0 in0b in1 in1b in2 in2b p 1 p 0 p 2 dspll lpf pd m in3/fb_in p 3 100 in3/fb_inb n 0 t 0 n 1 t 1 n 2 t 2 n 3 t 3 n 4 t 4 out2b vddo2 out2 r 2 external feedback path out1b vddo1 out1 r 1 out8b vddo8 out8 r 8 out9b vddo9 out9 r 9 figure 3.16. si5345 zero delay mode setup 3.9.14 output divider (r) synchronization all the output r dividers are reset to a known state during the power-up initialization period. this ensures consistent and repeatable phase alignment across all output drivers. resetting the device using the rstb pin or asserting the hard reset bit will have the same result. asserting the sync register bit provides another method of realigning the r dividers without resetting the device. 3.10 power management unused inputs and output drivers can be powered down when unused. consult the family reference manual and clockbuilder pro configuration utility for details. 3.11 in-circuit programming the si5345/44/42 is fully configurable using the serial interface (i 2 c or spi). at power-up the device downloads its default register val- ues from internal non-volatile memory (nvm). application specific default configurations can be written into nvm allowing the device to generate specific clock frequencies at power-up. writing default values to nvm is in-circuit programmable with normal operating power supply voltages applied to its v dd and v dda pins. the nvm is two time writable. once a new configuration has been written to nvm, the old configuration is no longer accessible. refer to the family reference manual for a detailed procedure for writing registers to nvm. si5345/44/42 rev d data sheet functional description silabs.com | smart. connected. energy-friendly. rev. 1.0 | 18
3.12 serial interface configuration and operation of the si5345/44/42 is controlled by reading and writing registers using the i 2 c or spi interface. the i2c_sel pin selects i 2 c or spi operation. communication with both 3.3 v and 1.8 v host is supported. the spi mode operates in either 4-wire or 3-wire. see the family reference manual for details. 3.13 custom factory preprogrammed parts for applications where a serial interface is not available for programming the device, custom pre-programmed parts can be ordered with a specific configuration written into nvm. a factory preprogrammed part will generate clocks at power-up. custom, factory-preprog- rammed devices are available. the clockbuilder pro custom part number wizard can be used to quickly and easily generate a custom part number for your configuration. in less than three minutes, you will be able to generate a custom part number with a detailed data sheet addendum matching your designs configuration. once you receive the confirmation email with the data sheet addendum, simply place an order with your local silicon labs sales representative. samples of your preprogrammed device will typically ship in about two weeks. 3.14 enabling features and/or configuration settings unavailable in clockbuilder pro for factory preprogrammed devices as with essentially all modern software utilities, clockbuilder pro is continually being updated and enhanced. by registering at www.si- labs.com , you will be notified about changes and their impact. this update process will ultimately enable clockbuilder pro users to ac- cess all features and register setting values documented in this data sheet and the family reference manual . however, if you must enable or access a feature or register setting value so that the device starts up with this feature or a register setting, but the feature or register setting is not yet available in cbpro, you must contact a silicon labs applications engineer for assis- tance. one example of this type of feature or custom setting is the customizable output amplitude and common voltages for the clock outputs. after careful review of your project file and requirements, the silicon labs applications engineer will email back your cbpro project file with your specific features and register settings enabled using what's referred to as the manual "settings override" feature of cbpro. "override" settings to match your request(s) will be listed in your design report file. examples of setting "overrides" in a cbpro design report are shown in the following table. table 3.3. setting overrides location name type target dec value hex value 0x04535[0] force_hold no nvm n/a 1 0x1 0x0b48[0:4] oof_div_clk_dis user opn&evb 0 0x00 si5345/44/42 rev d data sheet functional description silabs.com | smart. connected. energy-friendly. rev. 1.0 | 19
once you receive the updated design file, simply open it in cbpro. the device will begin operation after startup with the values in the nvm file. the flowchart for this process is shown in the following figure. do i need a pre-programmed device with a feature or setting which is unavailable in clockbuilder pro? no yes contact silicon labs technical support to submit & review your non-standard configuration request & cbpro project file configure device using cbpro load project file into cbpro and test receive updated cbpro project file from silicon labs with settings override generate custom opn in cbpro does the updated cbpro project file match your requirements? yes end: place sample order start bb p pmm f mp p contact silicon labs technical support at www.silabs.com/support/pages/default.aspx . si5345/44/42 rev d data sheet functional description silabs.com | smart. connected. energy-friendly. rev. 1.0 | 20
4. register map the register map is divided into multiple pages where each page has 256 addressable registers. page 0 contains frequently accessible registers, such as alarm status, resets, device identification, etc. other pages contain registers that need less frequent access such as frequency configuration, and general device settings. a high level map of the registers is shown in 6.2. high-level register map . refer to the family reference manual for a complete list of register descriptions and settings. silicon labs strongly recommends using clockbuilder pro to create and manage register settings. 4.1 addressing scheme the device registers are accessible using a 16-bit address that consists of an 8-bit page address plus an 8-bit register address. by default, the page address is set to 0x00. changing to another page is accomplished by writing to the "set page address" byte located at address 0x01 of each page. 4.2 high-level register map table 4.1. high-level register map 16-bit address content 8-bit page address 8-bit register address range 00 00 revision ids 01 set page address 02C0a device ids 0bC15 alarm status 17C1b intr masks 1c reset controls 1d finc, fdec control bits 2b spi (3-wire vs 4-wire) 2cCe1 alarm configuration e2Ce4 nvm controls fe device ready status 01 01 set page address 08C3a output driver controls 41C42 output driver disable masks fe device ready status 02 01 set page address 02C05 xtal frequency adjust 08C2f input divider (p) settings 30 input divider (p) update bits 47C6a output divider (r) settings 6bC72 user scratch pad memory fe device ready status si5345/44/42 rev d data sheet register map silabs.com | smart. connected. energy-friendly. rev. 1.0 | 21
16-bit address content 8-bit page address 8-bit register address range 03 01 set page address 02C37 multisynth divider (n0Cn4) settings 0c multisynth divider (n0) update bit 17 multisynth divider (n1) update bit 22 multisynth divider (n2) update bit 2d multisynth divider (n3) update bit 38 multisynth divider (n4) update bit 39C58 finc/fdec settings n0Cn4 59C62 output delay (t) settings fe device ready status 04 87 zero delay mode set up 05 0eC14 fast lock loop bandwidth 15C1f feedback divider (m) settings 2a input select control 2b fast lock control 2cC35 holdover settings 36 input clock switching mode select 38C39 input priority settings 3f holdover history valid data 06C08 00Cff reserved 09 01 set page address 1c zero delay mode settings 43 control i/o voltage select 49 input settings 10Cff 00Cff reserved si5345/44/42 rev d data sheet register map silabs.com | smart. connected. energy-friendly. rev. 1.0 | 22
5. electrical specifications table 5.1. recommended operating conditions 1 v dd = 1.8 v 5%, v dda = 3.3 v 5%, t a = C40 to 85 c parameter symbol min typ max unit ambient temperature t a C40 25 85 c junction temperature tj max 125 c core supply voltage v dd 1.71 1.80 1.89 v v dda 3.14 3.30 3.47 v clock output driver supply voltage v ddo 3.14 3.30 3.47 v 2.37 2.50 2.62 v 1.71 1.80 1.89 v status pin supply voltage v dds 3.14 3.30 3.47 v 1.71 1.80 1.89 v note: 1. all minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. typical val- ues apply at nominal supply voltages and an operating temperature of 25 c unless otherwise noted. si5345/44/42 rev d data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 1.0 | 23
table 5.2. dc characteristics v dd = 1.8 v 5%, v dda = 3.3 v 5%, v ddo = 1.8 v 5%, 2.5 v 5%, or 3.3 v 5%, t a = C40 to 85 c parameter symbol test condition min typ max unit core supply current 1, 2 , 3 i dd 135 260 ma i dda 120 130 ma output buffer supply current i ddox lvpecl output 4 @ 156.25 mhz 22 26 ma lvds output 4 @ 156.25 mhz 15 18 ma 3.3 v lvcmos output 5 @ 156.25 mhz 22 30 ma 2.5 v lvcmos output 5 @ 156.25 mhz 18 23 ma 1.8 v lvcmos output 5 @ 156.25 mhz 12 16 ma total power dissipation 6 p d si5345 1 900 1200 mw si5344 2 730 1000 mw si5342 3 670 950 mw notes: 1. si5345 test configuration: 7 x 2.5 v lvds outputs enabled at 156.25 mhz. excludes power in termination resistors. 2. si5344 test configuration: 4 x 2.5 v lvds outputs enabled at 156.25 mhz. excludes power in termination resistors. 3. si5342 test configuration: 2 x 2.5 v lvds outputs enabled at 156.25 mhz. excludes power in termination resistors. 4. differential outputs terminated into an ac-coupled 100 load. 5. lvcmos outputs measured into a 6 inch 50 pcb trace with 5 pf load. measurements were made in cmos3 mode. 50 50 100 out outb i ddo differential output test configuration 0.1 uf 0.1 uf 50 outa i ddo 5 pf lvcmos output test configuration 6 inch outb 6. detailed power consumption for any configuration can be estimated using clockbuilder pro when an evaluation board (evb) is not available. all evbs support detailed current measurements for any configuration. si5345/44/42 rev d data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 1.0 | 24
table 5.3. input clock specifications v dd = 1.8 v 5%, v dda = 3.3 v 5%, t a = C40 to 85 c parameter symbol test condition min typ max unit standard input buffer with differential or single-ended - ac coupled (in0/in0, in1/in1, in2/in2, in3/in3, fb_in/fb_in) input frequency range f in differential 0.008 750 mhz all single-ended signals (including lvcmos) 0.008 250 mhz voltage swing 1 v in differential ac-coupled f in < 250 mhz 100 1800 mvpp_se differential ac-coupled 250 mhz < f in < 750 mhz 225 1800 mvpp_se single-ended ac-coupled f in < 250 mhz 100 3600 mvpp_se slew rate 2, 3 sr 400 v/s duty cycle dc 40 60 % input capacitance c in 0.3 pf input resistance r in 16 k pulsed cmos input bufferdc coupled (in0, in1, in2, in4) 3 input frequency f in_pulsed_cm os 0.008 250 mhz input voltage v il C0.2 0.4 v v ih 0.8 v slew rate 2, 3 sr 400 v/s duty cycle dc 40 60 % minimum pulse width pw pulse input 1.6 ns input resistance r in 8 k refclk (applied to xa/xb) refclk frequency f in_ref full operating range. jit- ter performance may be reduced. 24.97 54.06 mhz range for best jitter. 48 54 mhz tcxo frequency for synce applications. jitter performance may be re- duced. 40 mhz input single-ended voltage swing v in_se 365 2000 mvpp_se input differential voltage swing v in_diff 365 2500 mvpp_diff slew rate 2 , 3 sr 400 v/s si5345/44/42 rev d data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 1.0 | 25
parameter symbol test condition min typ max unit input duty cycle dc 40 60 % note: 1. voltage swing is specified as single-ended mvpp. outxb outx vpp_se vpp_se vpp_diff = 2*vpp_se vcm vcm 2. imposed for jitter performance. 3. rise and fall times can be estimated using the following simplified equation: tr/tf 80-20 = ((0.8 C 0.2) x v in_vpp_se ) / sr. pulsed cmos mode is intended primarily for single-ended lvcmos input clocks < 1 mhz that must be dc-coupled because they have a duty cycle significantly less than 50%. a typical application example is a low-frequency video frame sync pulse. since the input thresholds (v il , v ih ) of this buffer are non-standard (0.4 and 0.8 v, respectively) refer to the input attenuator circuit for dc-coupled pulsed lvcmos in the family reference manual . otherwise, for standard lvcmos input clocks, use the standard differential or single-ended ac-coupled input mode. table 5.4. control input pin specifications v dd = 1.8 v 5%, v dda = 3.3 v 5%, v dds = 3.3 v 5%, 1.8 v 5%, t a = C40 to 85 c parameter symbol test condition min typ max unit si5345 control input pins (i2c_sel, in_sel[1:0], rstb, oeb, a1, sclk, a0/csb, finc, fdec, sda/sdio) input voltage v il 0.3 v ddio 1 v v ih 0.7 v ddio 1 v input capacitance c in 2 pf input resistance r in 20 k minimum pulse width pw rstb, finc and fdec 100 ns update rate t ur finc and fdec 1 s si5344/42 control input pins (i2c_sel, in_sel[1:0], rstb, oeb, a1, sclk, a0/csb, sda/sdio) input voltage v il 0.3 v ddio 1 v v ih 0.7 v ddio 1 v input capacitance c in 2 pf input resistance r in 20 k minimum pulse width pw rstb 100 ns note: 1. v ddio is determined by the io_vdd_sel bit. it is selectable as v dda or v dd . see the family reference manual for more details on the proper register settings. si5345/44/42 rev d data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 1.0 | 26
table 5.5. differential clock output specifications v dd = 1.8 v 5%, v dda = 3.3 v 5%, v ddo = 1.8 v 5%, 2.5 v 5%, or 3.3 v 5%, t a = C40 to 85 c parameter symbol test condition min typ max unit si5342/44/45 output frequency f out multisynth not used 0.0001 720 mhz 733.33 800.00 mhz 825 1028 mhz multisynth used 0.0001 720 mhz duty cycle dc f out < 400 mhz 48 52 % 400 mhz < f out < 1028 mhz 45 55 % output-output skew using same multisynth t sks outputs on same multisynth (measured at 712.5 mhz) 65 ps output-output skew between multisynths t skd outputs from different multisynths (measured at 712.5 mhz) 90 ps out-outb skew tsk_out measured from the positive to negative output pins 0 50 ps output voltage swing 1 vout v ddo = 3.3 v, 2.5 v, 1.8 v lvds 350 430 510 mvpp_se v ddo = 3.3 v, 2.5 v lvpecl 640 750 900 mvpp_se common mode voltage 1 , 2 (100 load line-to-line) vcm v ddo = 3.3 v lvds 1.10 1.2 1.3 v lvpecl 1.90 2.0 2.1 v v ddo = 2.5 v lvpecl lvds 1.1 1.2 1.3 v v ddo = 1.8 v sub-lvds 0.8 0.9 1.0 v rise and fall times (20% to 80%) tr/tf 100 150 ps differential output impedance zo 100 power supply noise rejec- tion 2 psrr 10 khz sinusoidal noise C101 dbc 100 khz sinusoidal noise C96 dbc 500 khz sinusoidal noise C99 dbc 1 mhz sinusoidal noise C97 dbc output-output crosstalk 3 xtalk si5345 C72 dbc si5342/44 C88 dbc si5345/44/42 rev d data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 1.0 | 27
parameter symbol test condition min typ max unit notes: 1. output amplitude and common-mode settings are programmable through register settings and can be stored in nvm. each out- put driver can be programmed independently. note that the maximum lvds single-ended amplitude can be up to 110 mv higher than the tia/eia-644 maximum. refer to the si5345/44/42 family reference manual for more suggested output settings. not all combinations of voltage amplitude and common mode voltages settings are possible. outxb outx vpp_se vpp_se vpp_diff = 2*vpp_se vcm vcm 2. measured for 156.25 mhz carrier frequency. 100 mvpp sinewave noise added to vddo = 3.3 v and noise spur amplitude meas- ured. 3. measured across two adjacent outputs, both in lvds mode, with the victim running at 155.52 mhz and the aggressor at 156.25 mhz. refer to an862: optimizing si534x jitter performance in next generation internet infrastructure systems for guidance on crosstalk optimization. note that all active outputs must be terminated when measuring crosstalk. si5345/44/42 rev d data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 1.0 | 28
table 5.6. lvcmos clock output specifications v dd = 1.8 v 5%, v dda = 3.3 v 5%, v ddo = 1.8 v 5%, 2.5 v 5%, or 3.3 v 5%, t a = C40 to 85 c parameter symbol test condition min typ max unit output frequency f out 0.0001 250 mhz duty cycle dc f out <100 mhz 48 52 % 100 mhz < f out < 250 mhz 45 55 % output-to-output skew t sk when outputs are on same multsynth. f out = 156.25 mhz 30 140 ps output voltage high 1, 2 , 3 v oh v ddo = 3.3 v outx_cmos_drv = 1 i oh = C10 ma v ddo x 0.85 v outx_cmos_drv = 2 i oh = C12 ma v ddo x 0.85 v outx_cmos_drv = 3 i oh = C17 ma v ddo x 0.85 v v ddo = 2.5 v outx_cmos_drv = 1 i oh = C6 ma v ddo x 0.85 v outx_cmos_drv = 2 i oh = C8 ma v ddo x 0.85 v outx_cmos_drv = 3 i oh = C11 ma v ddo x 0.85 v v ddo = 1.8 v outx_cmos_drv = 2 i oh = C4 ma v ddo x 0.85 v outx_cmos_drv = 3 i oh = C5 ma v ddo x 0.85 v output voltage low 1, 2, 3 v ol v ddo = 3.3 v outx_cmos_drv = 1 i ol = 10 ma v ddo x 0.15 v outx_cmos_drv = 2 i ol = 12 ma v ddo x 0.15 v outx_cmos_drv = 3 i ol = 17 ma v ddo x 0.15 v v ddo = 2.5 v outx_cmos_drv = 1 i ol = 6 ma v ddo x 0.15 v outx_cmos_drv = 2 i ol = 8 ma v ddo x 0.15 v outx_cmos_drv = 3 i ol = 11 ma v ddo x 0.15 v v ddo = 1.8 v outx_cmos_drv = 2 i ol = 4 ma v ddo x 0.15 v outx_cmos_drv = 3 i ol = 5 ma v ddo x 0.15 v lvcmos rise and fall times 3 (20% to 80%) tr/tf v ddo = 3.3v 400 600 ps v ddo = 2.5 v 450 600 ps v ddo = 1.8 v 550 750 ps si5345/44/42 rev d data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 1.0 | 29
parameter symbol test condition min typ max unit note: 1. driver strength is a register programmable setting and stored in nvm. options are outx_cmos_drv = 1, 2, 3. refer to the family reference manual for more details on register settings. 2. i ol /i oh is measured at v ol /v oh as shown in the dc test configuration. 3. a series termination resistor (rs) is recommended to help match the source impedance to a 50 pcb trace. a 5 pf capacitive load is assumed. the lvcmos outputs were set to outx_cmos_drv = 3, at 156.25 mhz. zs i ol /i oh v ol /v oh 50 out outb i ddo trace length 5 inches 50 4.7 pf 4.7 pf 56 499 499 56 ac test configuration 50 probe, scope 50 probe, scope dc block dc block table 5.7. output status pin specifications v dd = 1.8 v 5%, v dda = 3.3 v 5%, v dds = 3.3 v 5%, 1.8 v 5%, t a = C40 to 85 c parameter symbol test condition min typ max unit si5345 status output pins (lolb, intrb, sda/sdio 1 , sdo) output voltage v oh i oh = C2 ma v ddio 2 x 0.85 v v ol i ol = 2 ma v ddio 2 x 0.15 v si5344/42 status output pins (intrb, sda/sdio1 1 , sdo) output voltage v oh i oh = C2 ma v ddio 2 x 0.85 v v ol i ol = 2 ma v ddio 2 x 0.15 v si5344 status output pins (lolb, los_xaxbb) si5342 status output pins (lolb, los_xaxbb, los0b, los1b, los2b, los3b) output voltage v oh i oh = C2 ma v dds x 0.85 v v ol i ol = 2 ma v dds x 0.15 v notes: 1. the v oh specification does not apply to the open-drain sda/sdio output when the serial interface is in i 2 c mode or is unused with i2c_sel pulled high. vol remains valid in all cases. 2. v ddio is determined by the io_vdd_sel bit. it is selectable as v dda or v dd . see the family reference manual for more details on the proper register settings. si5345/44/42 rev d data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 1.0 | 30
table 5.8. performance characteristics v dd = 1.8 v 5%, v dda = 3.3 v 5%, t a = C40 to 85 c parameter symbol test condition min typ max unit vco frequency range f vco 13.5 14.4 ghz pll loop bandwidth program- ming range 1 f bw 0.1 4000 hz initial start-up time t start time from power-up to when the device gener- ates free-running clocks 30 45 ms pll lock time 2 t acq f in = 19.44 mhz 280 300 ms output delay adjustment t delay_frac f vco = 14 ghz 0.28 ps t delay_int 71.4 ps t range 9.14 ns por to serial interface ready 3 t rdy 15 ms jitter peaking j pk measured with a frequen- cy plan running a 25 mhz input, 25 mhz output, and a loop bandwidth of 4 hz 0.1 db jitter tolerance j tol compliant with g.8262 options 1 and 2 carrier frequency = 10.3125 ghz jitter modulation frequency = 10 hz 3180 ui pk-pk maximum phase transient during a hitless switch t switch only valid for a single au- tomatic switch between two input clocks at same frequency. 2.0 ns only valid for a single manual switch between two input clocks at same frequency. 1.3 ns pull-in range p 500 ppm si5345/44/42 rev d data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 1.0 | 31
parameter symbol test condition min typ max unit input-to-output delay variation t iodelay measured between a common 2 mhz input and 2 mhz output with differ- ent multisynths on the same unit. dspll bw = 4 khz 1.8 ns measured between a common 2 mhz input and 2 mhz output with differ- ent multisynths between units. dspll bandwidth = 4 khz 2.0 ns t zdelay delay between reference and feedback input with both clocks at 10 mhz and same slew rate. ref clock rise time must be <200 ps. 110 ps rms phase jitter 4 j gen integer mode 12 khz to 20 mhz 90 145 fs rms fractional mode 12 khz to 20 mhz 120 170 fs rms note: 1. actual loop bandwidth might be lower; please refer to cbpro for actual value for your frequency plan. 2. lock time can vary significantly depending on several parameters, such as bandwidths, lol tresholds, etc. for this case, lock time was measured with nominal and fastlock bandwidths set to 100 hz, lol set/clear thresholds of 6/0.6 ppm respectively, us- ing in0 as clock reference by removing the reference and enabling it again, then measuring the delta time between the first rising edge of the clock reference and the lol indicator deassertion. 3. measured as time from valid vdd/vdda rails (90% of their value) to when the serial interface is ready to respond to commands. 4. jitter generation test conditions: f in = 19.44 mhz, f out = 156.25 mhz lvpecl, loop bandwidth = 100 hz, f xtal = 48 mhz. table 5.9. i 2 c timing specifications (scl,sda) parameter symbol test condition standard mode 100 kbps fast mode 400 kbps unit min max min max scl clock frequency f scl 100 400 khz smbus timeout when timeout is enabled 25 35 25 35 ms hold time (repeated) start condition t hd:sta 4.0 0.6 s low period of the scl clock t low 4.7 1.3 s high period of the scl clock t high 4.0 0.6 s setup time for a repeated start condition t su:sta 4.7 0.6 s si5345/44/42 rev d data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 1.0 | 32
parameter symbol test condition standard mode 100 kbps fast mode 400 kbps unit min max min max data hold time t hd:dat 100 100 ns data setup time t su:dat 250 100 ns rise time of both sda and scl signals t r 1000 20 300 ns fall time of both sda and scl signals t f 300 300 ns setup time for stop condi- tion t su:sto 4.0 0.6 s bus free time between a stop and start condition t buf 4.7 1.3 s data valid time t vd:dat 3.45 0.9 s data valid acknowledge time t vd:ack 3.45 0.9 s figure 5.1. i 2 c serial port timing standard and fast modes si5345/44/42 rev d data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 1.0 | 33
table 5.10. spi timing specifications (4-wire) v dd = 1.8 v 5%, v dda = 3.3v 5%, t a = C40 to 85 c parameter symbol min typ max unit sclk frequency f spi 20 mhz sclk duty cycle t dc 40 60 % sclk period t c 50 ns delay time, sclk fall to sdo active t d1 12.5 18 ns delay time, sclk fall to sdo t d2 10 15 ns delay time, csb rise to sdo tri-state t d3 10 15 ns setup time, csb to sclk t su1 5 ns hold time, sclk fall to csb t h1 5 ns setup time, sdi to sclk rise t su2 5 ns hold time, sdi to sclk rise t h2 5 ns delay time between chip selects (csb) t cs 2 t c sclk csb sdi sdo t su1 t d 1 t su 2 t d2 t c t cs t d 3 t h2 t h1 figure 5.2. 4-wire spi serial interface timing si5345/44/42 rev d data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 1.0 | 34
table 5.11. spi timing specifications (3-wire) v dd = 1.8 v 5%, v dda = 3.3v 5%, t a = C40 to 85 c parameter symbol min typ max unit sclk frequency f spi 20 mhz sclk duty cycle t dc 40 60 % sclk period t c 50 ns delay time, sclk fall to sdio turn-on t d1 12.5 20 ns delay time, sclk fall to sdio next-bit t d2 10 15 ns delay time, csb rise to sdio tri-state t d3 10 15 ns setup time, csb to sclk t su1 5 ns hold time, csb to sclk fall t h1 5 ns setup time, sdi to sclk rise t su2 5 ns hold time, sdi to sclk rise t h2 5 ns delay time between chip selects (csb) t cs 2 t c sclk csb sdio t su1 t d1 t su2 t d 2 t c t cs t d3 t h 2 t h1 figure 5.3. 3-wire spi serial interface timing si5345/44/42 rev d data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 1.0 | 35
table 5.12. crystal specifications parameter symbol test condition min typ max unit crystal frequency range f xtal full operating range. jit- ter performance may be reduced. 24.97 54.06 mhz range for best jitter. 48 54 mhz load capacitance c l 8 pf crystal drive level d l 200 w equivalent series resistance shunt capacitance r esr c o refer to the si5345/44/42 reference manual to determine esr and shunt capac- itance. note: 1. refer to the si5345/44/42 reference manual for recommended 48 to 54 mhz crystals. the si5345/44/42 are designed to work with crystals that meet these specifications. table 5.13. thermal characteristics parameter symbol test condition 1 value unit si5345-64qfn thermal resistance junction to ambient ja still air 22 c/w air flow 1 m/s 19.4 c/w air flow 2 m/s 18.3 c/w thermal resistance junction to case jc 9.5 c/w thermal resistance junction to board jb 9.4 c/w jb 9.3 c/w thermal resistance junction to top center jt 0.2 c/w si5344, si5342-44qfn thermal resistance junction to ambient ja still air 22.3 c/w air flow 1 m/s 19.4 c/w air flow 2 m/s 18.4 c/w thermal resistance junction to case jc 10.9 c/w thermal resistance junction to board jb 9.3 c/w jb 9.2 c/w thermal resistance junction to top center jt 0.23 c/w note: 1. based on pcb dimension: 3" x 4.5" pcb thickness: 1.6 mm, pcb land/via: 36, number of cu layers: 4 si5345/44/42 rev d data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 1.0 | 36
table 5.14. absolute maximum ratings 1, 2 , 3 parameter symbol test condition value unit dc supply voltage v dd C0.5 to 3.8 v v dda C0.5 to 3.8 v v ddo C0.5 to 3.8 v v dds C0.5 to 3.8 v input voltage range v i1 4 in0Cin3/fb_in C0.85 to 3.8 v v i2 in_sel1, in_sel0, rstb, oeb, i2c_sel, finc, fdec, sdi, sclk, a0/csb, a1, sda/sdio C0.5 to 3.8 v v i3 xa/xb C0.5 to 2.7 v latch-up tolerance lu jesd78 compliant esd tolerance hbm 100 pf, 1.5 k 2.0 kv storage temperature range t stg C55 to 150 c maximum junction temperature in operation t jct 125 c soldering temperature (pb-free profile) 5 t peak 260 c soldering temperature time at t peak (pb-free profile) 5 t p 20C40 s note: 1. permanent device damage may occur if the absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. exposure to absolute maximum rating conditions for ex- tended periods may affect device reliability. 2. 64-qfn and 44-qfn packages are rohs-6 compliant. 3. moisture sensitivity level is msl2. for more packaging information, go to the silicon labs rohs information page . 4. the minimum voltage at these pins can be as low as C1.0 v when an ac input signal of 8 khz or greater is applied. see table 5.3 input clock specifications on page 25 for single-ended ac-coupled f in < 250 mhz. 5. the device is compliant with jedec j-std-020. si5345/44/42 rev d data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 1.0 | 37
6. typical application schematic cpu/npu fpga/asic/ switch 1g phy 1g phy 10g phy 10g phy 125 mhz (lvpecl) 125 mhz (lvpecl) 100 mhz (hcsl) 133.333 mhz (cmos) 83.333 mhz (cmos) 50 mhz (cmos) 156.25 mhz (lvds) 156.25 mhz (lvds) 2.048 mhz 19.44 mhz 125 mhz 100 mhz 156.525 mhz (lvds) 155.52 mhz (lvds) pcie 3.0 dspll si5345 multisynth multisynth multisynth multisynth multisynth figure 6.1. 10g ethernet data center switch and compute blade schematic si5345/44/42 rev d data sheet typical application schematic silabs.com smart. connected. energy-friendly. rev. 1.0 38
7. detailed block diagrams si5345 in_sel[1:0] dspll lpf pd optional external feedback vdd vdda 3 out2b vddo2 out2 vddo3 vddo0 out0b out0 r 2 out3b out3 r 3 out1b vddo1 out1 r 1 out5b vddo5 out5 vddo6 r 5 out6b out6 r 6 out4b vddo4 out4 r 4 out7b vddo7 out7 vddo8 r 7 out8b out8 r 8 r 0 status monitors intrb multi synth n 0n n 0d multi synth multi synth multi synth n 2n n 2d n 3n n 3d n 4n n 4d multi synth n 1n n 1d t 0 t 1 t 2 t 3 t 4 in0 in0b in1 in1b p 0n p 0d p 1n p 1d in2 in2b in3/fb_in in3/fb_inb p 3n p 3d p 2n p 2d out9b out9 r 9 vddo9 rstb oeb fdec finc m n m d sda/sdio a1/sdo sclk a0/csb i2c_sel spi/ i 2 c nvm lolb 48-54mhz xtal or ref clk osc xb xa p ref figure 7.1. si5345 block diagram si5345/44/42 rev d data sheet detailed block diagrams silabs.com smart. connected. energy-friendly. rev. 1.0 39
si5344 in_sel[1:0] dspll lpf pd optional external feedback in0 in0b in1 in1b p 0n p 0d p 1n p 1d in2 in2b in3/fb_in in3/fb_inb p 3n p 3d p 2n p 2d rstb oeb vdd vdda 4 2 out2b vddo2 out2 vddo3 vddo0 out0b out0 r 2 out3b out3 r 3 out1b vddo1 out1 r 1 r 0 multi synth n 0n n 0d multi synth multi synth n 2n n 2d n 3n n 3d multi synth n 1n n 1d t 0 t 1 t 2 t 3 sda/sdio a1/sdo sclk a0/csb i2c_sel spi/ i 2 c nvm m n m d status monitors los_xaxbb vdds lolb intrb 48-54mhz xtal or refclk osc xb xa p ref figure 7.2. si5344 block diagram si5345/44/42 rev d data sheet detailed block diagrams silabs.com smart. connected. energy-friendly. rev. 1.0 40
si5342 in_sel[1:0] dspll lpf pd optional external feedback in0 in0b in1 in1b p 0n p 0d p 1n p 1d in2 in2b in3/fb_in in3/fb_inb p 3n p 3d p 2n p 2d rstb oeb vdd vdda 4 2 vddo0 out0b out0 out1b vddo1 out1 r 1 r 0 multi synth n 0n n 0d multi synth n 1n n 1d t 0 t 1 m n m d status monitors los0b los1b los2b los_xaxbb sda/sdio a1/sdo sclk a0/csb i2c_sel spi/ i 2 c nvm los3b vdds lolb intrb 3 48-54mhz xtal or refclk osc xb xa p ref figure 7.3. si5342 block diagram si5345/44/42 rev d data sheet detailed block diagrams silabs.com smart. connected. energy-friendly. rev. 1.0 41
8. typical operating characteristics the phase noise plots below were taken under the following conditions: v dd = 1.8 v; v dda = 3.3 v; v dds = 3.3 v, 1.8 v; t a = 25 c. figure 8.1. input = 25 mhz; output = 625 mhz, 2.5 v lvds si5345/44/42 rev d data sheet typical operating characteristics silabs.com | smart. connected. energy-friendly. rev. 1.0 | 42
figure 8.2. input = 25 mhz; output = 156.25 mhz, 2.5 v lvds figure 8.3. input = 25 mhz; output = 155.52 mhz, 2.5 v lvds si5345/44/42 rev d data sheet typical operating characteristics silabs.com | smart. connected. energy-friendly. rev. 1.0 | 43
9. pin descriptions gnd pad in1 in1b in_sel0 in_sel1 rsvd rstb x1 xa xb x2 oeb intrb vdda in2 in2b sclk finc lolb vdd out6 out6b vddo6 out5 out5b vddo5 i2c_sel out4 out4b vddo4 out3 out3b vddo3 vddo7 out7b out7 vddo8 out8b out8 out9b out9 vddo9 vdd in3/fb_in in3b/fb_inb in0 in0b si5345 top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 a0/csb sda/sdio vdd rsvd rsvd vddo0 out0b out0 vddo1 out1b out1 fdec vddo2 out2b out2 a1/sdo rsvd rsvd gnd pad in1 in1b in_sel0 intrb x1 xa xb x2 oeb rstb vdda vdda in2 a0/csb sda/sdio a1/sdo out0b out0 vddo0 i2c_sel out1 out1b vddo1 vddo3 out3b out3 in3/fb_in in3b/fb_inb in0 in0b si5344 44qfn top view 1 2 3 4 5 6 7 8 9 10 33 32 31 30 29 28 27 26 25 24 12 13 14 15 16 17 18 19 20 21 44 43 42 41 40 39 38 37 36 35 vdd out2 out2b vddo2 vdds lolb los_xaxbb vdd in_sel1 in2b 11 23 nc 22 vdd vdd 34 sclk gnd pad in1 in1b in_sel0 intrb x1 xa xb x2 oeb rstb vdda vdda in2 a0/csb sda/sdio a1/sdo out0b out0 vddo0 i2c_sel out1 out1b vddo1 vdds los2b los3b in3/fb_in in3b/fb_inb in0 in0b si5342 44qfn top view 1 2 3 4 5 6 7 8 9 10 33 32 31 30 29 28 27 26 25 24 12 13 14 15 16 17 18 19 20 21 44 43 42 41 40 39 38 37 36 35 vdd los1b los0b vdds vdds lolb los_xaxbb vdd in_sel1 in2b 11 23 nc 22 vdd vdd 34 sclk ddcc g gmpm op gp silabs.com smart. connected. energy-friendly. rev. 1.0 44
table 9.1. si5345/44/42 pin descriptions pin name pin number pin type 1 function si5345 si5344 si5342 inputs xa 8 5 5 i crystal input. input pins for external crystal (xtal). alternatively these pins can be driven with an external reference clock (refclk). an internal register bit selects xtal or refclk mode. default is xtal mode. xb 9 6 6 i x1 7 4 4 i xtal shield. connect these pins directly to the xtal ground pins. x1, x2 and the xtal ground pins should be separated from the pcb ground plane. refer to the si5345/44/42 family refer- ence manual for layout guidelines. these pins should be left dis- connected when connecting xa/xb pins to an external reference clock (refclk). x2 10 7 7 i in0 63 43 43 i clock inputs. these pins accept an input clock for synchronizing the device. they support both differential and single-ended clock signals. refer to 3.7.6 input configuration and terminations for input termination options. these pins are high-impedance and must be terminated externally. the negative side of the differen- tial input must be grounded through a capacitor when accepting a single-ended clock. in0b 64 44 44 i in1 1 1 1 i in1b 2 2 2 i in2 14 10 10 i in2b 15 11 11 i in3/fb_in 61 41 41 i clock input 3/external feedback input. by default these pins are used as the fourth clock input (in3/in3b). they can also be used as the external feedback input (fb_in/fb_inb) for the op- tional zero delay mode. see 3.9.13 zero delay mode for details on the optional zero delay mode. in3b/fb_inb 62 42 42 i si5345/44/42 rev d data sheet pin descriptions silabs.com | smart. connected. energy-friendly. rev. 1.0 | 45
table 9.2. si5345/44/42 pin descriptions pin name pin number pin type 1 function si5345 si5344 si5342 outputs out0 24 20 20 o output clocks. these output clocks support a programmable signal swing and common mode voltage. desired output signal format is configurable using register control. termination recom- mendations are provided in 3.9.3 differential output terminations and 3.9.4 lvcmos output terminations . unused outputs should be left unconnected. out0b 23 19 19 o out1 28 25 25 o out1b 27 24 24 o out2 31 31 o out2b 30 30 o out3 35 36 o out3b 34 35 o out4 38 o out4b 37 o out5 42 o out5b 41 o out6 45 o out6b 44 o out7 51 o out7b 50 o out8 54 o out8b 53 o out9 59 o out9b 58 o serial interface i2c_sel 39 38 38 i i 2 c select 2 . this pin selects the serial interface mode as i 2 c (i2c_sel = 1) or spi (i2c_sel = 0). this pin is internally pulled up by a ~ 20 k resistor to the voltage selected by the io_vdd_sel register bit. sda/sdio 18 13 13 i/o serial data interface 2 this is the bidirectional data pin (sda) for the i 2 c mode, or the bidirectional data pin (sdio) in the 3-wire spi mode, or the input data pin (sdi) in 4-wire spi mode. when in i 2 c mode, this pin must be pulled-up using an external resistor of at least 1 k . no pull-up resistor is needed when is spi mode. tie low when un- used. a1/sdo 17 15 15 i/o address select 1/serial data output 2 in i 2 c mode, this pin functions as the a1 address input pin and does not have an internal pull-up or pull-down resistor. in 4-wire spi mode this is the serial data output (sdo) pin and drives high to the voltage selected by the io_vdd_sel bit. leave discon- nected when unused. si5345/44/42 rev d data sheet pin descriptions silabs.com | smart. connected. energy-friendly. rev. 1.0 | 46
pin name pin number pin type 1 function si5345 si5344 si5342 sclk 16 14 14 i serial clock input 2 this pin functions as the serial clock input for both i 2 c and spi modes. when in i 2 c mode, this pin must be pulled-up using an external resistor of at least 1 k. no pull-up resistor is needed when in spi mode. tie high or low when unused. a0/csb 19 16 16 i address select 0/chip select 2 this pin functions as the hardware controlled address a0 in i 2 c mode. in spi mode, this pin functions as the chip select input (ac- tive low). this pin is internally pulled-up by a ~20 k resistor and can be left unconnected when not in use. control/status intrb 12 33 33 o interrupt 2 this pin is asserted low when a change in device status has oc- curred. it should be left unconnected when not in use. rstb 6 17 17 i device reset 2 active low input that performs power-on reset (por) of the de- vice. resets all internal logic to a known state and forces the de- vice registers to their default values. clock outputs are disabled during reset. this pin is internally pulled-up and can be left un- connected when not in use. oeb 11 12 12 i output enable 2 this pin disables all outputs when held high. this pin is internally pulled low and can be left unconnected when not in use. lolb 47 o loss of lock (si5345) 2 this output pin indicates when the dspll is locked (high) or out- of-lock (low). it can be left unconnected when not in use. 27 27 o loss of lock (si5344/42) 3 this output pin indicates when the dspll is locked (high) or out- of-lock (low). it can be left unconnected when not in use. los0b 30 o loss of signal for in0 3 this pin indicate a loss of clock at the in0 pin when low. los1b 31 o loss of signal for in1 3 this pin indicate a loss of clock at the in1 pin when low. los2b 35 o loss of signal for in2 3 this pin indicate a loss of clock at the in2 pin when low. los3b 36 o loss of signal for in3 3 this pin indicate a loss of clock at the in3 pin when low. los_xaxbb 28 28 o loss of signal on xa/xb pins 3 this pin indicates a loss of signal at the xa/xb pins when low. si5345/44/42 rev d data sheet pin descriptions silabs.com | smart. connected. energy-friendly. rev. 1.0 | 47
pin name pin number pin type 1 function si5345 si5344 si5342 finc 48 i frequency increment pin 2 this pin is used to step-up the output frequency of a selected out- put. the affected output and its frequency change step size is register configurable. this pin is internally pulled low and can be left unconnected when not in use. fdec 25 i frequency decrement pin 2 this pin is used to step-down the output frequency of a selected output. the affected output driver and its frequency change step size is register configurable. this pin is internally pulled low and can be left unconnected when not in use. in_sel0 3 3 3 i input reference select 2 the in_sel[1:0] pins are used in manual pin controlled mode to select the active clock input as shown in table 3.1 manual input selection using in_sel[1:0] pins on page 8. these pins are in- ternally pulled low. in_sel1 4 37 37 i rsvd 5 reserved these pins are connected to the die. leave disconnected. 20 21 55 56 nc 22 22 no connect these pins are not connected to the die. leave disconnected. power vdd 32 21 21 p core supply voltage the device operates from a 1.8 v supply. a 1.0 f bypass capac- itor should be placed very close to this pin. see the si5345/44/42 family reference manual for power supply filtering recommenda- tions. 46 32 32 p 60 39 39 p 40 40 p vdda 13 8 8 p core supply voltage 3.3 v this core supply pin requires a 3.3 v power source. a 1 f by- pass capacitor should be placed very close to this pin. see the si5345/44/42 family reference manual for power supply filtering recommendations. 9 9 p vdds 26 26 p status output voltage the voltage on this pin determines vol/voh on the si5342/44 lol_a and lol_b outputs. connect to either 3.3 v or 1.8 v. a 1.0 f bypass capacitor should be placed very close to this pin. 29 p 34 p si5345/44/42 rev d data sheet pin descriptions silabs.com | smart. connected. energy-friendly. rev. 1.0 | 48
pin name pin number pin type 1 function si5345 si5344 si5342 vddo0 22 18 18 p output clock supply voltage supply voltage (3.3 v, 2.5 v, 1.8 v) for outn, outn outputs. for unused outputs, leave vddo pins unconnected. an alternative option is to connect the vddo pin to a power supply and disable the output driver to minimize current consumption. vddo1 26 23 23 p vddo2 29 29 p vddo3 33 34 p vddo4 36 p vddo5 40 p vddo6 43 p vddo7 49 p vddo8 52 p vddo9 57 p gnd pad p ground pad this pad provides connection to ground and must be connected for proper operation. use as many vias as practical, and keep the via length to an internal ground plane as short as possible. note: 1. i = input, o = output, p = power. 2. the io_vdd_sel control bit (0x0943 bit 0) selects 3.3 v or 1.8 v operation. 3. the voltage on the vdds pin(s) determines 3.3 v or 1.8 v operation. 4. refer to the family reference manual for more information on register setting names. 5. all status pins except i2c and spi are push-pull. si5345/44/42 rev d data sheet pin descriptions silabs.com | smart. connected. energy-friendly. rev. 1.0 | 49
10. package outlines 10.1 si5345 9x9 mm 64-qfn package diagram the following figure illustrates the package details for the si5345. the table lists the values for the dimensions shown in the illustration. figure 10.1. 64-pin quad flat no-lead (qfn) table 10.1. package dimensions dimension min nom max a 0.80 0.85 0.90 a1 0.00 0.02 0.05 b 0.18 0.25 0.30 d 9.00 bsc d2 5.10 5.20 5.30 e 0.50 bsc e 9.00 bsc e2 5.10 5.20 5.30 l 0.30 0.40 0.50 aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.10 note: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline mo-220. 4. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. si5345/44/42 rev d data sheet package outlines silabs.com | smart. connected. energy-friendly. rev. 1.0 | 50
10.2 si5344 and si5342 7x7 mm 44-qfn package diagram the following figure illustrates the package details for the si5344 and si5342. the table lists the values for the dimensions shown in the illustration. figure 10.2. 44-pin quad flat no-lead (qfn) table 10.2. package dimensions dimension min nom max a 0.80 0.85 0.90 a1 0.00 0.02 0.05 b 0.18 0.25 0.30 d 7.00 bsc d2 5.10 5.20 5.30 e 0.50 bsc e 7.00 bsc e2 5.10 5.20 5.30 l 0.30 0.40 0.50 aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.10 note: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline mo-220. 4. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. si5345/44/42 rev d data sheet package outlines silabs.com | smart. connected. energy-friendly. rev. 1.0 | 51
11. pcb land pattern the following figure illustrates the pcb land pattern details for the devices. the table lists the values for the dimensions shown in the illustration. si5345 si5344 and si5342 figure 11.1. pcb land pattern si5345/44/42 rev d data sheet pcb land pattern silabs.com | smart. connected. energy-friendly. rev. 1.0 | 52
table 11.1. pcb land pattern dimensions dimension si5345 (max) si5344/42 (max) c1 8.90 6.90 c2 8.90 6.90 e 0.50 0.50 x1 0.30 0.30 y1 0.85 0.85 x2 5.30 5.30 y2 5.30 5.30 notes: general 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. this land pattern design is based on the ipc-7351 guidelines. 3. all dimensions shown are at maximum material condition (mmc). least material condition is calculated based on a fabrication allowance of 0.05 mm. solder mask design 1. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 1. a stainless steel, laser-cut and electropolished stencil with trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness should be 0.125 mm (5 mils). 3. the ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 4. a 3x3 array of 1.25 mm square openings on 1.80 mm pitch should be used for the center ground pad. card assembly 1. a no-clean, type-3 solder paste is recommended. 2. the recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. si5345/44/42 rev d data sheet pcb land pattern silabs.com | smart. connected. energy-friendly. rev. 1.0 | 53
12. top marking figure 12.1. si5345/44/42 top marking table 12.1. top marking explanation line characters description 1 si534fg- base part number and device grade for any-frequency, any-output, jitter cleaning clock (single pll): f = 5: 10-output si5345: 64-qfn f = 4: 4-output si5344: 44-qfn f = 2: 2-output si5342: 44-qfn g = device grade (a, b, c, d). see 2. ordering guide for more information. C = dash character. 2 rxxxxx-gm r = product revision. (refer to 2. ordering guide for latest revision). xxxxx = customer specific nvm sequence number. optional nvm code as- signed for custom, factory pre-programmed devices. characters are not included for standard, factory default configured devices. see 2. ordering guide for more information. -gm = package (qfn) and temperature range (C40 to +85 c) 3 yywwtttttt yyww = characters correspond to the year (yy) and work week (ww) of package assembly. tttttt = manufacturing trace code. 4 circle w/ 1.6 mm (64-qfn) or 1.4 mm (44-qfn) diameter pin 1 indicator; left-justified e4 tw pb-free symbol; center-justified tw = taiwan; country of origin (iso abbreviation) si5345/44/42 rev d data sheet top marking silabs.com | smart. connected. energy-friendly. rev. 1.0 | 54
13. device errata log in or register at www.silabs.com to access the device errata document. si5345/44/42 rev d data sheet device errata silabs.com | smart. connected. energy-friendly. rev. 1.0 | 55
14. document change list 14.1 revision 1.0 july 15, 2016 ? initial release. si5345/44/42 rev d data sheet document change list silabs.com | smart. connected. energy-friendly. rev. 1.0 | 56
table of contents 1. features list ............................... 1 2. ordering guide ..............................2 3. functional description ............................4 3.1 frequency configuration ..........................4 3.2 dspll loop bandwidth ..........................4 3.3 fastlock feature .............................4 3.4 modes of operation ............................4 3.4.1 initialization and reset ..........................5 3.4.2 freerun mode .............................5 3.4.3 lock acquisition mode ..........................5 3.4.4 locked mode .............................5 3.4.5 holdover mode .............................6 3.5 external reference (xa/xb) .........................6 3.6 digitally controlled oscillator (dco) mode ....................7 3.7 inputs (in0, in1, in2, in3) ..........................7 3.7.1 manual input switching (in0, in1, in2, in3) ...................8 3.7.2 automatic input selection (in0, in1, in2, in3) ..................8 3.7.3 hitless input switching ..........................8 3.7.4 ramped input switching ..........................8 3.7.5 glitchless input switching .........................8 3.7.6 input configuration and terminations .....................9 3.7.7 synchronizing to gapped input clocks ..................... 10 3.8 fault monitoring ............................. 10 3.8.1 input los detection ........................... 11 3.8.2 xa/xb los detection .......................... 11 3.8.3 oof detection ............................. 11 3.8.3.1 precision oof monitor ......................... 12 3.8.3.2 fast oof monitor ........................... 12 3.8.4 lol detection ............................. 12 3.8.5 interrupt pin (intrb) ........................... 13 3.9 outputs ................................ 13 3.9.1 output crosspoint ............................ 14 3.9.2 output signal format ........................... 14 3.9.3 differential output terminations ....................... 15 3.9.4 lvcmos output terminations ....................... 15 3.9.5 programmable common mode voltage for differential outputs ............ 15 3.9.6 lvcmos output impedance selection ..................... 16 3.9.7 lvcmos output signal swing ....................... 16 3.9.8 lvcmos output polarity ......................... 16 3.9.9 output enable/disable .......................... 16 3.9.10 output driver state when disabled ..................... 16 3.9.11 synchronous output disable feature ..................... 16 3.9.12 output skew control (t 0 C t 4 ) ....................... 17 table of contents 57
3.9.13 zero delay mode ............................ 18 3.9.14 output divider (r) synchronization ...................... 18 3.10 power management ........................... 18 3.11 in-circuit programming .......................... 18 3.12 serial interface ............................. 19 3.13 custom factory preprogrammed parts ..................... 19 3.14 enabling features and/or configuration settings unavailable in clockbuilder pro for factory pre- programmed devices ........................... 19 4. register map .............................. 21 4.1 addressing scheme ............................ 21 4.2 high-level register map .......................... 21 5. electrical specifications .......................... 23 6. typical application schematic ........................ 38 7. detailed block diagrams .......................... 39 8. typical operating characteristics ...................... 42 9. pin descriptions ............................. 44 10. package outlines ............................ 50 10.1 si5345 9x9 mm 64-qfn package diagram ................... 50 10.2 si5344 and si5342 7x7 mm 44-qfn package diagram ............... 51 11. pcb land pattern ............................ 52 12. top marking .............................. 54 13. device errata .............................. 55 14. document change list .......................... 56 14.1 revision 1.0 .............................. 56 table of contents 58
http://www.silabs.com silicon laboratories inc. 400 west cesar chavez austin, tx 78701 usa clockbuilder pro one-click access to timing tools, documentation, software, source code libraries & more. available for windows and ios (cbgo only). www.silabs.com/cbpro timing portfolio www.silabs.com/timing sw/hw www.silabs.com/cbpro quality www.silabs.com/quality support and community community.silabs.com disclaimer silicon laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the silicon laboratories products. characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "typical" parameters provided can and do vary in different applications. application examples described herein are for illustrative purposes only. silicon laboratories reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. silicon laboratories shall have no liability for the consequences of use of the information supplied herein. this document does not imply or express copyright licenses granted hereunder to design or fabricate any integrated circuits. the products are not designed or authorized to be used within any life support system without the specific written consent of silicon laboratories. a "life support system" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal injury or death. silicon laboratories products are not designed or authorized for military applications. silicon laboratories products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons. trademark information silicon laboratories inc.? , silicon laboratories?, silicon labs?, silabs? and the silicon labs logo?, bluegiga?, bluegiga logo?, clockbuilder?, cmems?, dspll?, efm?, efm32?, efr, ember?, energy micro, energy micro logo and combinations thereof, "the world?s most energy friendly microcontrollers", ember?, ezlink?, ezradio?, ezradiopro?, gecko?, isomodem?, precision32?, proslic?, simplicity studio?, siphy?, telegesis, the telegesis logo?, usbxpress? and others are trademarks or registered trademarks of silicon laborato - ries inc. arm, cortex, cortex-m3 and thumb are trademarks or registered trademarks of arm holdings. keil is a registered trademark of arm limited. all other products or brand names mentioned herein are trademarks of their respective holders.

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